Freescale Semiconductor /SKEAZ1284 /MSCAN /CANBTR1

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Interpret as CANBTR1

SAMP=0, TSEG2=000, TSEG1=0000

Description

MSCAN Bus Timing Register 1

Fields

TSEG1	Time Segment 1 0 (0000): 1 Tq clock cycle (not valid) 1 (0001): 2 Tq clock cycles (not valid) 2 (0010): 3 Tq clock cycles (not valid) 3 (0011): 4 Tq clock cycles 14 (1110): 15 Tq clock cycles 15 (1111): 16 Tq clock cycles
TSEG2	Time Segment 2 0 (000): 1 Tq clock cycle (not valid) 1 (001): 2 Tq clock cycles 2 (010): 3 Tq clock cycles 3 (011): 4 Tq clock cycles 4 (100): 5 Tq clock cycles 5 (101): 6 Tq clock cycles 6 (110): 7 Tq clock cycles 7 (111): 8 Tq clock cycles
SAMP	Sampling 0 (0): One sample per bit. 1 (1): Three samples per bit. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).

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